View ISL78215_4927059.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Improved Industry Standard Single-Ended Current Mode PWM Controller
ISL78215
The ISL78215 family of adjustable frequency, low power, pulse width modulating (PWM) current mode controllers is designed for a wide range of power conversion applications including boost, flyback, and isolated output configurations. Peak current mode control effectively handles power transients and provides inherent overcurrent protection. This advanced BiCMOS design is pin compatible with the industry standard 384x family of controllers and offers significantly improved performance. Features include low operating current, 60A start-up current, adjustable operating frequency to 2MHz, and high peak current drive capability with 20ns rise and fall times. The ISL78215 is fully TS16949 compliant and tested to AEC-Q100 specifications.
ISL78215
Features
* 1A MOSFET Gate Driver * 60A Start-up Current, 100A Maximum * 25ns Propagation Delay Current Sense to Output * Fast Transient Response with Peak Current Mode Control * Adjustable Switching Frequency to 2MHz * 20ns Rise and Fall Times with 1nF Output Load * Trimmed Timing Capacitor Discharge Current for Accurate Deadtime/Maximum Duty Cycle Control * High Bandwidth Error Amplifier * Tight Tolerance Voltage Reference Over Line, Load, and Temperature * Tight Tolerance Current Limit Threshold * Pb-Free (RoHS Compliant) * TS16949 Compliant * AEC-Q100 Tested
Applications*(see page 10)
* Automotive Power * Telecom and Datacom Power * Wireless Base Station Power * File Server Power * Industrial Power Systems * PC Power Supplies * Isolated Buck and Flyback Regulators * Boost Regulators
Pin Configuration
ISL78215 (8 LD MSOP) TOP VIEW
COMP 1 FB 2 CS 3 RTCT 4 8 VREF 7 VDD 6 OUT 5 GND
August 16, 2010 FN7673.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL78215
Pin Description
PIN 1 SYMBOL COMP DESCRIPTION COMP is the output of the error amplifier and the input of the PWM comparator. The control loop frequency compensation network is connected between the COMP and FB pins. The output voltage feedback is connected to the inverting input of the error amplifier through this pin. The non-inverting input of the error amplifier is internally tied to a reference voltage. This is the current sense input to the PWM comparator. The range of the input signal is nominally 0V to 1.0V and has an internal offset of 100mV. This is the oscillator timing control pin. The operational frequency and maximum duty cycle are set by connecting a resistor, RT, between VREF and this pin and a timing capacitor, CT, from this pin to GND. The oscillator produces a sawtooth waveform with a programmable frequency range up to 2.0MHz. The charge time, tC, the discharge time, tD, the switching frequency, f, and the maximum duty cycle, Dmax, can be calculated from Equations 1, 2, 3 and 4: t C 0.583 * RT * CT 0.0083 * RT - 4.3 - RT * CT * ln ---------------------------------------------- 0.0083 * RT - 2.4 (EQ. 1)
2
FB
3 4
CS RTCT
t
D
(EQ. 2)
f = 1 (tC + tD)
D=t C *f
(EQ. 3) (EQ. 4)
Figure 4 may be used as a guideline in selecting the capacitor and resistor values required for a given frequency. 5 6 7 GND OUT VDD GND is the power and small signal reference ground for all functions. This is the drive output to the power switching device. It is a high current output capable of driving the gate of a power MOSFET with peak currents of 1.0A. VDD is the power connection for the device. The total supply current will depend on the load applied to OUT. Total IDD current is the sum of the operating current and the average output current. Knowing the operating frequency, f, and the MOSFET gate charge, Qg, the average output current can be calculated in Equation 5: I OUT = Qg x f (EQ. 5)
To optimize noise immunity, bypass VDD to GND with a ceramic capacitor as close to the VDD and GND pins as possible. 8 VREF The 5.00V reference voltage output. +1.0/-1.5% tolerance over line, load and operating temperature. Bypass to GND with a 0.1F to 3.3F capacitor to filter this output as needed.
Ordering Information
PART NUMBER (Notes 2, 3) ISL78215AUZ ISL78215AUZ-T (Note 1) PART MARKING 78215 78215 TEMP RANGE (C) -40 to +105 -40 to +105 PACKAGE (Pb-free) 8 Ld MSOP 8 Ld MSOP PKG. DWG. # M8.118 M8.118
1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL78215. For more information on MSL please see techbrief TB363.
2
FN7673.0 August 16, 2010
Functional Block Diagram
VREF 5.00V ENABLE VREF FAULT + VREF UV COMPARATOR 4.65V 4.80V
VDD UVLO COMPARATOR + BG + GND A 2.5V A = 0.5 VDD OK
VREF
PWM COMPARATOR CS 100mV + + -
+ BG
3
FB COMP VREF RTCT
FN7673.0 August 16, 2010
ISL78215
ERROR AMPLIFIER + -
2R
1.1V CLAMP R
ISL78215 Q T Q OUT SQ
2.6V 0.7V ON OSCILLATOR COMPARATOR + 8.4mA ON
RQ RESET DOMINANT
CLOCK
Typical Application - 48V Input Dual Output Flyback
CR5 +3.3V T1 VIN+ R3 C4 CR4 CR2 C17 C19 + C22 + C20 RETURN CR6 36V TO 75V C1 R1 C3 Q1 C6 R16 U2 R17 R19 C14 R18 R21 C21 +C15 + C16
+1.8V
4
VINR6 Q3 VR1
FN7673.0 August 16, 2010
C2
C5
ISL78215
R4
R22 R27 U3
C13
R15
R20 U4 R26 COMP CS FB VREF VDD OUT
RTCT GND ISL78215 R10
CR1
C12 C8 R13 C11
Typical Application - Boost Converter
R8 C10
CR1 VIN+ L1 +VOUT + C2 C3
5
Q1 R4 RETURN R5 C9 C1 R1 R2 U1 COMP ISL78215 FB C4 CS RTCT VREF VDD OUT GND R7 VIN+ C8 R6
ISL78215
R3
C5 C6
C7
VINFN7673.0 August 16, 2010
ISL78215
Absolute Maximum Ratings
Supply Voltage, VDD . . . . . . . . . . . . . GND - 0.3V to +20.0V OUT . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VDD + 0.3V Signal Pins . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 6.0V Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1A ESD Rating Human Body Model (Tested per JESD22-A11) . . . . . 2500V Machine Model (Tested per JESD22-C101) . . . . . . . . . 75V Charged Device Model (Tested per JESD22-A115) . . 1500V
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) MSOP Package (Notes 4, 5) . . . . . . 170 60 Maximum Junction Temperature . . . . . . . . -55C to +150C Maximum Storage Temperature Range . . . -65C to +150C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . -40C to +105C Supply Voltage Range (Typical, Note 6). . . . . . . .7.5V to 18V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. For JC, the "case temp" location is taken at the package top center. 6. All voltages are with respect to GND.
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to "Functional Block Diagram" on page 3 and "Typical Application" schematics on page 4 and 5. VDD = 15V (Note 10), Rt = 10k, Ct = 3.3nF, TA = -40 to +105C, Typical values are at TA = +25C. Boldface limits apply over the operating temperature range, -40C to +105C. TEST CONDITIONS MIN (Note 7) 6.5 6.1 VDD < START Threshold (Note 8) Includes 1nF GATE loading Over line (VDD = 12V to 18V), load, temperature TA = +125C, 1000 hours (Note 9) 4.925 4.40 4.60 50 -20 5 VCS = 1V VCS = 0V (Note 9) VCS = 0V (Note 9) -1.0 95 0.80 0.91 0 < VCS < 910mV, VFB = 0V (Note 9) 2.5 TYP 7.0 6.6 0.4 60 3.3 4.1 5.000 5 4.65 4.80 165 100 1.15 0.97 3.0 MAX (Note 7) 7.5 6.9 100 4.0 5.5 5.050 4.85 VREF - 0.05 250 1.0 105 1.30 1.03 3.5 UNITS V V V A mA mA V mV V V mV mA mA A mV V V V/V
PARAMETER UNDERVOLTAGE LOCKOUT START Threshold STOP Threshold Hysteresis Start-up Current, IDD Operating Current, IDD Operating Supply Current, ID REFERENCE VOLTAGE Overall Accuracy Long Term Stability Fault Voltage VREF Good Voltage Hysteresis Current Limit, Sourcing Current Limit, Sinking CURRENT SENSE Input Bias Current CS Offset Voltage COMP to PWM Comparator Offset Voltage Input Signal, Maximum Gain, ACS = VCOMP/VCS
6
FN7673.0 August 16, 2010
ISL78215
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to "Functional Block Diagram" on page 3 and "Typical Application" schematics on page 4 and 5. VDD = 15V (Note 10), Rt = 10k, Ct = 3.3nF, TA = -40 to +105C, Typical values are at TA = +25C. Boldface limits apply over the operating temperature range, -40C to +105C. (Continued) TEST CONDITIONS (Note 9) (Note 9) (Note 9) VFB = VCOMP VFB = 0V VCOMP = 1.5V, VFB = 2.7V VCOMP = 1.5V, VFB = 2.3V VFB = 2.3V VFB = 2.7V Frequency = 120Hz, VDD = 12V to 18V (Note 9) Initial, TJ = +25C T = +25C (f18V - f12V)/f12V (Note 9) MIN (Note 7) 60 3.5 2.475 -1.0 1.0 -0.4 4.80 0.4 60 TYP 25 90 5 2.514 -0.2 80 MAX (Note 7) 40 2.55 1.0 VREF 1.0 UNITS ns dB MHz V A mA mA V V dB
PARAMETER CS to OUT Delay ERROR AMPLIFIER Open Loop Voltage Gain Unity Gain Bandwidth Reference Voltage FB Input Bias Current COMP Sink Current COMP Source Current COMP VOH COMP VOL PSRR OSCILLATOR Frequency Accuracy Frequency Variation with VDD Temperature Stability Amplitude, Peak-to-Peak RTCT Discharge Voltage Discharge Current OUTPUT Gate VOH Gate VOL Peak Output Current Rise Time Fall Time PWM Maximum Duty Cycle Minimum Duty Cycle NOTES:
49 -
52 0.2 1.9 0.7 8.4 1.0 1.0 1.0 20 20 48 -
55 1.0 5 9.5 2.0 2.0 40 40
kHz % % V V mA V V A ns ns %
RTCT = 2.0V VDD to OUT, IOUT = -200mA OUT to GND, IOUT = 200mA COUT = 1nF (Note 9) COUT = 1nF (Note 9) COUT = 1nF (Note 9)
7.2 47 -
0
%
7. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 8. This is the VDD current consumed when the device is active but not switching. Does not include gate drive current. 9. Limits established by characterization and are not production tested. 10. Adjust VDD above the start threshold and then lower to 15V.
7
FN7673.0 August 16, 2010
ISL78215
Typical Performance Curves
1.02 NORMALIZED FREQUENCY NORMALIZED VREF -10 20 50 80 110 1.01 1.00 0.99 0.98 0.97 -40
1.001 1.000 0.999 0.998 0.997 0.996 0.995 -40 -25 -10 5 20 35 50 65 80 95 110
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 1. FREQUENCY vs TEMPERATURE
FIGURE 2. REFERENCE VOLTAGE vs TEMPERATURE
NORMALIZED EA REFERENCE
1.002 FREQUENCY (kHz)
103 100pF 100 220pF 330pF 470pF 1.0nF 10 2.2nF 3.3nF 4.7nF 20 30 40 50 60 70 80 90 100
1.000
0.998
0.996
0.994 -40 -25 -10 5 20 35 50 65 80 95 110 TEMPERATURE (C)
1 10
RT (k)
FIGURE 3. EA REFERENCE vs TEMPERATURE
FIGURE 4. RESISTANCE FOR CT CAPACITOR VALUES GIVEN
Functional Description
Features
The ISL78215 current mode PWMs make an ideal choice for low-cost flyback and forward topology applications. With its greatly improved performance over industry standard parts, it is the obvious choice for new designs or existing designs which require updating.
Soft-Start Operation
Soft-start must be implemented externally. One method, illustrated in Figure 5, clamps the voltage on COMP.
VREF ISL78215
Oscillator
The ISL78215 controllers have a sawtooth oscillator with a programmable frequency range to 2MHz, which can be programmed with a resistor from VREF and a capacitor to GND on the RTCT pin. (Please refer to Figure 4 for the resistor and capacitance required for a given frequency.)
COMP
GND
FIGURE 5. SOFT-START
8
FN7673.0 August 16, 2010
ISL78215
Gate Drive
The ISL78215 is capable of sourcing and sinking 1A peak current. To limit the peak current through the IC, an optional external resistor may be placed between the totem-pole output of the IC (OUT pin) and the gate of the MOSFET. This small series resistor also damps any oscillations caused by the resonant tank of the parasitic inductances in the traces of the board and the FET's input capacitance. Slope compensation may be added to the CS signal shown in Figure 7.
RTCT ISL78215
VREF
Slope Compensation
For applications where the maximum duty cycle is less than 50%, slope compensation may be used to improve noise immunity, particularly at lighter loads. The amount of slope compensation required for noise immunity is determined empirically, but is generally about 10% of the full scale current feedback signal. For applications where the duty cycle is greater than 50%, slope compensation is required to prevent instability. The minimum amount of slope compensation required corresponds to 1/2 the inductor downslope. Adding excessive slope compensation, however, results in a control loop that behaves more as a voltage mode controller than as a current mode controller.
CS SIGNAL (V) DOWNSLOPE CURRENT SENSE SIGNAL
CS
FIGURE 7. SLOPE COMPENSATION
Fault Conditions
A Fault condition occurs if VREF falls below 4.65V. When a Fault is detected, OUT is disabled. When VREF exceeds 4.80V, the Fault condition clears, and OUT is enabled.
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the device. A good ground plane must be employed. A unique section of the ground plane must be designated for high di/dt currents associated with the output stage. VDD should be bypassed directly to GND with good high frequency capacitors.
TIME
FIGURE 6. CURRENT SENSE DOWNSLOPE
9
FN7673.0 August 16, 2010
ISL78215
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE 8/16/10 REVISION FN7673.0 Initial Release. CHANGE
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL78215 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 10
FN7673.0 August 16, 2010
ISL78215
Package Outline Drawing
M8.118
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE Rev 3, 3/10
5 3.00.05 A 8 D DETAIL "X"
1.10 MAX
SIDE VIEW 2 4.90.15
0.09 - 0.20
3.00.05 5
PIN# 1 ID 1 2 B 0.65 BSC TOP VIEW
0.95 REF
GAUGE PLANE
0.25
0.55 0.15 H 0.85010 DETAIL "X" C SEATING PLANE 0.25 - 0.036 0.08 M C A-B D SIDE VIEW 1 0.10 0.05 0.10 C
33
(5.80) (4.40) (3.00) NOTES: 1. Dimensions are in millimeters. 2. Dimensioning and tolerancing conform to JEDEC MO-187-AA and AMSEY14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. 4. Plastic interlead protrusions of 0.15mm max per side are not included. 5. Dimensions are measured at Datum Plane "H". 6. Dimensions in ( ) are for reference only.
(0.65) (0.40) (1.40)
TYPICAL RECOMMENDED LAND PATTERN
11
FN7673.0 August 16, 2010

▲Up To Search▲

Price & Availability of ISL78215

	To Download ISL78215 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .